Annunciator and control system with specific application to internal combustion engines



3,535,545 FIG ES D. W. SCHLICHER AND CON ANNUNCIATOR TROL SYSTEM WITHSPECI APPLICATION TO INTERNAL COMBUSTION ENGIN Filed July 24. 1951 2Sheets-Sheet l f T FIG. 2

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ATTORNEY o. w. SCHLICHER 3,535,545 ANNUNCIATOR AND CONTROL SYSTEM WITHSPECIFIC APPLICATION TO INTERNAL COMBUSTION ENGINES Filed July 24. 19672 Sheets-Shasta 228 zsl- TRUTH TABLE INPUTS OUTPUTS J R P o' I 0 11 Q o0-(o+n)(o+ow; I v

FIG-6 TRUTH TABLE I .lNPUTS OUTPUT a s M o o o I Mn v FIG] I WMAI v IOUTPUT NOR , INVENTOR v mam-a DAVID w. SCHLICHER BYWGQWW ATTORNEY UnitedStates Patent 3,535,545 ANNUNCIATOR AND CONTROL SYSTEM WITH SPECIFICAPPLICATION TO INTERNAL COM- BUSTION ENGINES David W. Schlicher,Minneapolis, Minn., assignor to Electric Machinery Mfg. Company,Minneapolis, Minn., a corporation of Minnesota Filed July 24, 1967, Ser.No. 655,591 Int. Cl. H03k 19/20 US. Cl. 307215 2 Claims ABSTRACT OF THEDISCLOSURE An annunciator and control system including annunciatorsadapted to indicate faults in internal combustion engine operation and acontrol means for shutting down the system or correcting the faulttogether with lockout means for rendering the first to act annunciatoroperative and to lock out all the other annunciators prior to resettingof the system.

FIELD OF THE INVENTION Annunciators adapted to indicate faults in theoperation of internal combustion engines together with a control forShutting down the engine or correcting the fault.

PRIOR ART Annunciators in which the circuits therefor are independent ofone another.

SUMMARY OF THE INVENTION The invention resides in providingintercommunicating circuits between the annunciators and by means ofwhich the operation of one annunciator looks out all the otherannunciators thereby indicating only the first fault to occur.

SPECIFICATION To simplify the drawings and description of the inventionsymbolic logic has been used and Boolean expressions for the variousoutputs are employed along with truth tables. In the instant casenegative logic is employed and NOR gates and inverters have been used. Alogical 1 thus represents a low voltage state While a logical 0represents a high voltage state. It will however become evident thatother gates may be used.

In the drawings:

FIG. 1 is a schematic diagram using Boolean gates and inverters anddisclosing the invention in use for controlling the operation of adiesel engine.

FIG. 2 is a table showing the initial logic states of the various logicdevices of the circuits disclosed in FIG. 1.

FIG. 3 is a schematic diagram of the engine starting annunciator sectionof the invention.

FIG. 4 is a truth table for the inputs and outputs of the circuits shownin FIG. 3.

FIG. 5 is a schematic diagram of the engine crank termination andlockout section.

FIG. 6 discloses the truth table for the crank termination circuit shownin FIG. 5.

FIG. 7 is a wiring diagram of the components of one of the NOR gatesused in the invention.

As an example of the use of the invention it is assumed that theinvention is to be used with a diesel engine. For controlling theoperation of the engine one method is to control the flow of fuel to thesame and electrically operated valve not illustrated may be used for thepurpose. Such an engine requires a starting motor for turning over theengine and in the event that the engine does not start the usualpractice is to shut off the starting motor, Wait for a short time andmake another try. If after several ice tries the engine will not startit is customary to cease trying and ascertain and correct the fault. Inaddition numerous other engine faults may occur such as oil failure,excessive temperature at various localities such as bearings, windings,etc., low voltage, low speed, low fuel, etc. One fault such as improperlubrication may cause several other faults such as reduced speed, lowvoltage, and temperature increase, thus making it impossible to readilyascertain the cause of the faults. The instant invention overcomes thisdisadvantage by maintaining the indication of the first fault to occurand locking out the indications of all the other faults. To simplify thedisclosure only the indicating means for failure of the engine to startand oil failure have been disclosed though it will be readilycomprehended that as many faults as desired may be indicated by the useof additional fault circuits.

The structure disclosed comprises a lubrication fault sensitive sectionA which operates a lubrication fault indicating section B. Similarly anengine overcrank detection section C operates an overcrank faultindicating section D. Both the sections B and D operate a controlsection G which stops the engine Whenever B or D indicate a fault. Amultivibrator section E provides alternate crank-rest timing periods andenergizes the starting motor through the crank control section F.Section H controls crank termination and lockout after the enginestarts.

The section A comprises a normally closed oil pressure switch S1 whichis connected to ground by means of a conductor 72. This switch isfurther connected by means of a conductor 73 to an inverter 74 which inturn is connected by a conductor 75 to input 2 of a two input NOR gate76. Input 1 of this gate is connected to a time delay device 70 by meansof conductor 71 which in turn is connected to inverter 68 by conductor69. A conductor 16 connects inverter 68 to a centrifugally operatedswitch S2 which is grounded by conductor 18.

The section B includes three two input NOR gates 219, 221, and 223. Theoutput of gate 76 is connected by a conductor 287 to input 1 of gate219. The output of gate 219 is connected by means of a conductor 220 tothe input 2 of gate 223. Input 1 of this gate is connected by aconductor 222 to the output of gate 221 while the output of gate 223 isconnected by means of conductor 226 to inverter 229. The output of gate23 is further connected by means of conductors 224 and 225 to the inputs2 of gates 219 and 221. This inverter is connected by means of aconductor 232 to the base of a transistor 233. A conductor 234 connectsthe emitter of said transistor to ground. The collector of saidtransistor is connected by means of a conductor 235 to a lamp 236 whichin turn is connected by means of a conductor 237 to a source of directcurrent V. The lamp 236 constitutes the lubrication fault annunciator.

The overcrank detection section C consists of two inverters 82 and 86and a binary counter 84. This counter may be of ordinary constructionand has not been shown in detail. Inverter 82 is connected by means ofconductor 83 to the binary counter 84. This counter is connected by aconductor 85 to inverter 86.

The overcrank indicator D includes 3 NOR gates 119, 121 and 123. Theinput 1 of NOR gate 121 is connected to the conductor 231 which in turnis connected to input 1 of NOR gate 221, Input 2 of NOR gate 121 isconnected by means of a conductor 125 to the output of NOR gate 123. Theinput 2 of NOR gate 119 is connected by means of a conductor 124 to theoutput of NOR gate 123. Input 1 of NOR gate 119 is connected by means ofconductor 187 to inverter 86 previously referred to. The output of NORgate 119 is connected by means of a conductor 120 to the input 1 of NORgate 123. The output of NOR gate 121 is connected by means of aconductor 122 to the input 2 of NOR gate 123. The output of NOR gate 123is connected by means of a conductor 126 to an inverter 129. Thisinverter is connected by means of a conductor 132 to the base of atransistor 133. The emitter of this transistor is connected by aconductor 134 to ground. The collector of transistor 133 is connected bymeans of a conductor 135 to a lamp 136 which serves as the annunciatorfor the section D of the invention. This lamp is further connected byconductor 137 to a source of voltage V.

The crank-rest timing section E utilizes a multivibrator which may be ofordinary construction. This multivibrator utilizes a NOR gate 58 having3 inputs. Input 1 of this gate is connected by means of a conductor 46to a resistor 47 which in turn is connected by a conductor 48 to ground.Input 2 of the gate 58 is connected by means of a conductor 7 to theconductor 16 previously referred to. Input 3 of this gate is connectedby means of a conductor 65 to an inverter 66 which is connected by aconductor 67 to the conductor 231. The output of NOR gate 58 isconnected by means of a conductor 59 to a capacitor 60 which in turn isconnected by means of a conductor 61 to a resistor 63. This resistor isconnected by a conductor 64 to a source of voltage VA. The conductor 61is connected by means of another conductor 62 to the base of atransistor '54. The emitter of this transistor is connected by means ofa conductor 51 to a resistor 50 which in turn is connected by means of aconductor 49 to ground. The emitter is further connected to inverter 53by means of conductor 52. The collector of transistor 54 is connected bymeans of conductor 55 to resistor 56. This resistor is connected by aconductor 57 to said source of voltage VA. Said inverter 53 is furtherconnected by means of conductor 40 to resistor 42 which is connected bya conductor 43 to capacitor 44. This capacitor is further connected tosaid input 1 of NOR gate 58.

The crank control section F utilizes a two input NOR gate 87. Input 2 ofthis gate is connected by a conductor 41 to conductor 40 previouslyreferred to. The output of NOR gate 87 is connected by a conductor 77 toan inverter 78. This inverter is connected by means of a con ductor 79to a solenoid and other mechanism 80 for cranking the engine.

The control section G of the invention utilizes a triple input NOR gate27. Input 1 of this gate is connected by means of a conductor 128 toconductor 126. Input 3 of this gate is connected by means of a conductor228 to the conductor 226. The output of gate 27 is connected by means ofa conductor 30 to an inverter 38. Inverter 38 is connected by aconductor 39 to a solenoid and mechanism 88 for controlling the flow offuel to the engine. A conductor 31 is connected to conductor 30 and alsoto conductor 231.

For starting up the system a switch S3 is employed which is connected bymeans of a conductor 92 to ground. The switch S3 is further connected bya conductor 91 to an inverter 89 which is connected by means of aconductor 90 to the input 2 of NOR gate 27.

The crank termination section H includes two inverters 8 and 9. Theoutput of the inverter 9 is connected by means of a conductor 13 to theinput 2 of a NOR gate 10. The output of inverter 8 is similarlyconnected by means of a conductor 19 to input 1 of said NOR gate 10. Theoutput of NOR gate is connected by means of a conductor 14 to the input2 of a NOR gate 11. The output of this NOR gate is connected by means ofa conductor 21 to an inverter 12. A conductor 15 connects the output ofinverter 12 to the input of inverter 9. The input 1 of NOR gate 11 isconnected by means of a conductor 17 to conductor 16 previously referredto.

The operation of the invention is as follows: The table shown in FIG. 2gives the initial state of all of the logic elements shown in FIG. 1. Tocrank the engine switch S3 is closed which applies a logical l toinverters 8 and 89. Referring to the diagram in FIG. 5 and the truthtable in FIG. 6 it is seen that with the input at switch S3 changingfrom 0 to 1 and with the input at switch S2 equal to 0 the output ofinverter 12 remains in its previous state which was a logical 0. Thelogical 1 input to NOR 89 causes the following changes of state tooccur: NOR 89 output becomes a logical 0 which in effect makes the Pinput of FIG. 3 equal to a logical 0 and unlocks all the fault indicatorcircuits. Specifically in FIG. 1, input 2 of NOR 27 is a logical O whichchanges the output to logical 1. This output is applied to inverter 38which changes state and causes the solenoid and accessories 88 to beenergized and changes inputs 1 of NOR 121 and 221 to a logical 0. Thisnow places control of NOR 123 and 223 upon a change of state of NOR 119and 219 respectively and this will occur any time a fault indication isobtained. The logical 1 output of Nor 27 is also applied to inverter 66which applies a logical 0 to input 3 of NOR 58 and starts the astablemultivibrator E. The output of the multivibrator is applied to the input2 of NOR 87 where a logical 0 represents a period of cranking andlogical 1 represents a period of resting. Cranking is accomplished byapplying the changing output of NOR 87 to inverter 78 which controls thecrank energization. The crank period which is the order of 10 to 20seconds is controlled by resistor 63 and capacitor 60. The rest periodis determined by values of resistor 42 and capacitor 44. These alternatecrankrest periods continue until the engine starts or until the binarycounter 84 counts the present number of cranks at which time a logical 0is applied to inverter 86 which in turn applies a logical 1 to input 1of NOR 119. This represents the R input to NOR 119 of FIGS. 1 and 3 andthe truth table of FIG. 4 shows that the indication output Q now goes toa logical l and the control output 73+? goes to a logical O.

The indication output from NOR 123 is applied to inverter 129 whichcauses the overcrank lamp 136 to light and to input 2 of NOR 119 and NOR121 which latches on this fault circuit. The control output from NOR 27deenergizes the engine through inverter 38 and locks out thelow-oil-pressure fault circuit A through NOR 221. This can be seen moreclearly by referring to the truth table in FIG. 4. It will becomeevident with respect to the over crank circuit that the input P is 0, soafter R once becomes 1, the input remains latched in the 1 state. Withreference to the low-oil-pressure fault circuit, the

"P input is the Q output of the over crank circuit and since this is 1the Q output remains in the same state regardless of the R input.

The operation just described was based on the assumption that there wasno engine start. In the event of a start, speed switch S2 closes whenthe engine reaches the desired speed. A logical l is then applied toinput 1 of NOR 11, input 2 of NOR 58 and inverter 68. This terminatescranking, stops the multivibrator and starts the time delay deviceoperating. The oil pressure switch S1 must now open before time device70 times out or NOR 76 would change state and indicate a lowoil-pressure fault. Operation would then be the same as with theovercrank fault except that the function of the two fault,

circuits would be reversed. With switch S1 opening before the time delaydevice 70 times out NOR 76 would not change state and the engine wouldcontinue running until shut down was desired and switch S3 was opened oruntil some monitored fault shut it down.

Although only two fault circuits are shown, any number of similar faultcircuits could be added with the outputs feeding the correspondingnumber of inputs of NOR 27.

The advantages of the invention are manifest. The first fault to occurwould indicate the origin of the same, and said fault corrected.Frequently one fault causes one or more other faults and an indicationof the first fault and correction thereof might remove one or more ofthe other faults.

Changes in the specific form of the invention, as herein described, maybe made within the scope of what is claimed without departing from thespirit of the invention.

Having described the invention, what is claimed as new and desired to beprotected by Letters Patent is:

1. A logic annunciator and control circuit comprising:

(a) a control section having two inputs and an output,

(b) a first fault indicating section having two inputs and an output,

(c) a first fault sensitive section having an output connected to one ofthe inputs of said first fault indicating section,

(d) a second fault indicating section having two inputs and an output,

(e) a second fault sensitive section having an output connected to oneof the inputs of said second fault indicating section,

(f) the other input of the first fault indicating section designated bythe letter R being connected to the output of the control section,

(g) the other input of the second fault indicating section designated bythe letter P being also connected to the output of the control section,

(h) the outputs of both fault indicating sections designated by theletter Q being respectively connected to the inputs of the controlcircuit whereby,

(i) the relation of the sections of the annunciator control circuit isindicated by the equation 2. A logic annunciator and control circuitaccording to claim 1 in which:

(a) the first fault indicating section comprises (b) a first NOR gatehaving first and second inputs and an output, (0) a second gate havingfirst and second inputs and an output and (d) a third NOR gate havingfirst and second inputs and an output,

(e) said control section including a single NOR gate having first andsecond inputs and an output,

(if) said first fault sensitive section being connected to the firstinput of said first gate of said first fault indicating section,

(g) the output of the gate of the control section being connected to thefirst input of the second gate of the first fault indicating section,

(h) the second input of the first and second gates of the first faultindicating section being both connected to the first input of the gateof the control section and (i) the inputs and outputs of the gates ofthe second fault indicating section are connected with respect to eachother and to the second fault sensitive section and the control sectionin the same manner as the gates of the first fault section wereconnected.

References Cited Goodell, Foundations of Computing Machinery, Journal ofComputing Systems, January 1953, vol. 1, No. 2 (pp. 97, 98).

Grabbe et al., Handbook of Automation Computation and Control, vol. 2,October 1959 (pp. 17-08, 17-11).

Lode, Realization of a Universal Decision Element, Journal of ComputingSystems, June 1952, vol. 1, No. 1 (pp. 19, 20).

Zehner et al., IBM Tech. Dis. Bu1., vol. 2, No. 6, April 1960 (p. 103).

DONALD D. FORRER, Primary Examiner D. M. CARTER, Assistant Examiner US.Cl. X.R. 307-207 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTIONPatent No 3 S35 545 October 20 1970 Q David W. Schlicher It is certifiedthat error appears in the above identified patent and that said LettersPatent are hereby corrected as shown below:

Column 4, line 34 and column 5, line 29,

Q+P should read Q+P Signed and sealed this 30th day of March 1971.

(SEAL) Attest:

EDWARD M.FLETCHER,JR.

WILLIAM E. SCHUYLER, JR.

